1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and a repair method thereof.
2. Description of the Related Art
Semiconductor memory devices including Dynamic Random Access Memory (DRAM) may use a stacked structure where a plurality of memory chips are piled up vertically. Semiconductor memory devices of this type are referred to as three-dimensional (3D) stack package semiconductor memory devices. With the stack package structure, semiconductor memory devices may have a high integration degree and large capacity, where the size of the semiconductor memory devices may be reduced and an interface with high frequency band width may be enabled.
Here, the stacked memory chips include memory cells that are each formed of a cell transistor and a cell capacitor. Among memory cells of a memory chip, a memory cell with defect (“a defective cell”) may occur. The presence of a defective cell decreases the yield of a semiconductor memory device. Here, memory cell defects may occur as semiconductor memory devices become highly integrated, shrink in sizes, increase in capacity, and operate at an increasingly lower power source level, where the line widths of circuitry are decreased in proportion and a number of the procedural steps and the complexity thereof are increased.
In repairing a defective cell and increasing the yield of a semiconductor memory device, a spare memory cell for each memory chip and is often provided to replace a defective cell with the spare memory cell. More specifically, a spare cell (“a redundancy cell” hereinafter) is prepared before a test is performed on memory cells to detect a defective memory cell and then after the test, any defective cell is repaired by being replaced with the redundancy cell.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device 100 includes first to fourth memory chips 110, 120, 130 and 140 that are stacked vertically. The relative roles of the first to fourth memory chips 110, 120, 130 and 140 with respect to each other are decided according to the stacking sequence. For example, the fourth memory 140 that is stacked in the lowermost position and coupled with the external circuits operates as a master chip, and the other chips sequentially stacked on top of the fourth memory 140 (the first to third memory chips 110, 120 and 130) serve as slave chips which perform a desired operation under the control of the master chip.
According to an example, since the internal structures of the first to fourth memory chips 110, 120, 130 and 140 are all the same, the first memory chip 110 is representatively described hereinafter.
The first memory chip 110 includes a plurality of first memory cells 112A and 112B for storing data, a plurality of first redundancy cells 114A and 114B for replacing defective cells among the multiple first memory cells 112A and 112B, and first fuse circuits 116A and 116B for programming an address for switching the address of a defective cell with the address of a redundancy cell. Here, the first fuse circuits 116A and 116B include a plurality of fuses, and the address program is performed through a fuse cutting process.
Hereinafter, a method for repairing the conventional semiconductor memory device having the above-described structure is described with reference to FIG. 2.
FIG. 2 is a flowchart describing a method for repairing the conventional semiconductor memory device.
Referring to FIG. 2, in the state that the first to fourth memory chips 110, 120, 130 and 140 are fabricated, the first to fourth memory chips 110, 120, 130 and 140 are tested at a wafer level to find out where there is a defective cell or not in step S10. For example, data is stored in the first memory cells 112A and 112B included in the first memory chip 110 and then the stored data is read back. In this way, the first memory cells 112A and 112B are tested to determine whether there is a defective cell or not.
In step S20, after the test, the addresses of defective cells are stored for each memory chip based on the test result.
In this state, the fuses included in the first fuse circuits 116A and 116B of the first memory chip 110 are programmed with an address in response to the stored addresses for each memory chip. For example, the address programming may be performed by performing a fuse cutting process with a laser. When the address programming is performed through the fuse cutting process, the defective cells existing in the first memory cells 112A and 112B may be replaced with the first redundancy cells 114A and 114B. Accordingly, the first redundancy cells 114A and 114B may be used instead of the defective cells in the first memory cells 112A and 112B in performing operations directed to the defective cells.
Subsequently, the fuses included in the second to fourth memory chips 120, 130 and 140 are sequentially programmed in steps S40, 50 and 60 using the same method for programming the fuses included in the first memory chip 110.
Subsequently, at step S70, the first to fourth memory chips 110, 120, 130 and 140 are vertically stacked and thus, the fabrication of the semiconductor memory device 100 is completed.
However, since the process of programming addresses in the fuses included in the first to fourth memory chips 110, 120, 130 and 140 is performed for each memory chip in the conventional semiconductor memory device 100 by accessing each memory chip separately in programming its respective fuses, the cost and time for the process thereof may be significant.